1. Field of the Invention
The present invention relates to synchronizers and, more particularly, to a high speed synchronizer suitable for simultaneously initializing rising edge triggered flip-flops and falling edge triggered flip-flops that can be located in the same clock domain or in different clock domains.
2. Description of the Related Art
A clock domain contains a group of flip-flops that are driven by the same primary clock signal. A logic circuit can include any number of different clock domains. For example, one group of flip-flops can be driven by a first clock signal, while another group of flip-flops can be driven by a second clock signal.
In many cases, the clock signals driving the different clock domains are totally asynchronous to each other. In other words, each primary clock signal can have a different frequency and/or different clock phase and/or different clock width (duty cycle) in comparison to the other primary clock signals.
Many digital logic applications utilize rising edge triggered flip-flops and falling edge triggered flip-flops. These flip-flops can be of several types, including D flip-flops, RS flip-flops, JK flip-flops and toggle flip-flops. For example, a D flip-flop is a logic device that has a D input, a clock input and Q/QZ outputs. A D flip-flop can also have an asynchronous set input and/or an asynchronous clear input. In operation, a D flip-flop stores the logic state on its D input in response to a clock signal on its clock input. Furthermore, a D flip-flop outputs the stored logic state on its Q/QZ outputs, where QZ is the logical complement (inverse) of Q.
A rising edge triggered D flip-flop is a flip-flop that outputs the logic state on its D input in response to a rising edge on its clock input. Similarly, a falling edge triggered D flip-flop is a flip-flop that outputs the logic state on its D input in response to a falling edge on its clock input. Of course, rising edge triggered flip-flops and falling edge triggered flip-flops can be located in the same clock domain or in different clock domains.
Furthermore, the Q output of a rising/falling edge triggered D flip-flop can be initialized to the logic zero state by applying a clear pulse to the flip-flop clear input. The clear pulse is usually asynchronous to the clock pulse. Thus, if the clear pulse is applied by a sufficient time before a given clock pulse, the flip-flop Q output will be set to the logic zero state prior to the next clock pulse.
Similarly, the Q output of a rising/falling edge triggered D flip-flop can be initialized to the logic one state by applying a set pulse to the flip-flop set input. The set pulse is usually asynchronous to the clock pulse. Thus, if the set pulse is applied by a sufficient time before a given clock pulse, the flip-flop Q output will be set to the logic one state prior to the next clock pulse.
FIGS. 1A–1D illustrate the timing of a prior-art clear signal that is being applied to a pair of target flip-flops that are rising edge triggered. As shown in FIGS. 1A–1D, the target flip-flops receive a clock signal CLK and a clear signal CLR, which is asynchronous to the clock signal CLK. Furthermore, the first target flip-flop outputs a signal Q1 that represents the value stored in the first target flip-flop, while the second target flip-flop outputs a signal Q2 that represents the value stored in the second target flip-flop.
As shown in FIGS. 1A–1B, the clear signal CLR rises between the first and second clock pulses of the clock signal CLK, a time TOA before the rising edge of the second clock pulse. In response, the Q1 output of the first target flip-flop is initialized to a logic zero, a propagation delay time T1 following the rising edge of the clear signal CLR. Similarly, the Q2 output of the second target flip-flop is also initialized to a logic zero, a propagation delay time T2 following the rising edge of the clear signal CLR.
Since the propagation delay times T1 and T2 are both less than the time TOA, the first and second target flip-flops will both be in the cleared state before the next rising edge of the clock signal CLK.
FIGS. 2A–2D also show the timing of a prior-art clear signal that is being applied to a pair of target flip-flops that are rising edge triggered. As shown in FIGS. 2A–2D, the target flip-flops receive a clock signal CLK and a clear signal CLR, which is asynchronous to the clock signal CLK. Furthermore, the first target flip-flop outputs a signal Q1 that represents the value stored in the first target flip-flop, while the second target flip-flop outputs a signal Q2 that represents the value stored in the second target flip-flop.
As shown in FIGS. 2A–2B, the clear signal CLR rises between the first and second clock pulses of the clock signal CLK, a time TOB before the rising edge of the second clock pulse. In response, the Q1 output of the first target flip-flop is initialized to a logic zero, a propagation delay time T1 following the rising edge of the clear signal CLR. Similarly, the Q2 output of the second target flip-flop is also initialized to a logic zero, a propagation delay time T2 following the rising edge of the clear signal CLR.
Referring to FIGS. 2A–2D, it can be seen that propagation delay time T1 is shorter than the time TOB, whereas propagation delay time T2 is longer than the time TOB. As a result, the Q1 output of the first target flip-flop falls to zero before the rising edge of the next clock pulse, whereas the Q2 output of the second target flip-flop falls to zero after the rising edge of the next clock pulse. Therefore, both target flip-flops are not initialized to zero prior to the next rising edge of the clock signal CLK.
In order to insure that all of the rising edge triggered flip-flops in a given clock domain are properly cleared, the time interval from the rising edge of the clear signal to the next rising edge of the clock signal must be greater than the longest clear signal propagation delay time for the slowest flip-flop. Therefore, in order to insure that there is sufficient time to initialize each flip-flop in a given clock domain, the rising edge of the clear signal is usually synchronized to, and nearly aligned with, the rising edge of the clock signal.
FIG. 3 shows a block diagram that illustrates a prior-art, rising edge triggered clear signal synchronizer 300. This circuit insures that the rising edge of the clear signal is synchronized to, and nearly aligned with, the rising edge of the clock signal.
As shown in FIG. 3, synchronizer 300 includes a first flip-flop FF1 and a second flip-flop FF2 that are connected as a two bit shift register. (Two flip-flops are employed, instead of one, in order to greatly reduce the probability that the second flip-flop output will go into a meta-stable state). Flip-flop FF1 includes a D input that receives a clear signal CLR, a clock input that receives a clock signal CLK, and a Q output that generates a flip-flop output signal QA.
Furthermore, flip-flop FF2 includes a D input that receives the QA signal from the Q output of flip-flop FF1, a clock input that receives the clock signal CLK, and a Q output that generates a synchronized clear signal CLR_SYNC.
FIGS. 4A–4F show timing diagrams that illustrate the operation of synchronizer 300. As shown in FIGS. 4A–4F, the clear signal CLR rises to a logic high between the first and second clock pulses of the clock signal CLK. In particular, the clear signal CLR rises to a logic high at a time T0 before the rising edge of the second clock pulse. Assuming that the setup time of flip-flop FF1 has been met, flip-flop FF1 will capture the logic high on its D input on the rising edge of the second clock pulse. Thus, at a propagation delay time after the clock signal CLK rises, flip-flop FF1 will output the QA signal as a logic high on its Q output.
Referring to FIGS. 4A–4F, flip-flop FF2 captures the logic high on its D input on the rising edge of the third pulse of the clock signal CLK. Thus flip-flop FF2 outputs the synchronized clear signal CLR_SYNC as a logic high on its Q output, at a propagation delay time after the clock signal CLK rises. As shown in FIGS. 4A–4F, the clear signal CLR_SYNC is synchronized to, and nearly aligned with, the rising edge of the clock signal CLK.
The synchronized clear signal CLR_SYNC is then fed into the clear input of a target pair of rising edge triggered flip-flops. The first target flip-flop outputs a signal Q1 that represents the value stored in the first target flip-flop. Similarly, the second target flip-flop outputs a signal Q2 that represents the value stored in the second target flip-flop.
As shown in FIGS. 4D–4F, in response to the rising edge of the synchronized clear signal CLR_SYNC, the Q1 output from the first target flip-flop is initialized to a logic zero at a propagation delay time T1 after the rising edge of the clock signal CLK. Similarly, in response to the rising edge of the synchronized clear signal CLR_SYNC, the Q2 output from the second target flip-flop is initialized to a logic zero at a propagation delay time T2 after the rising edge of the clock signal CLK.
Thus, as shown in FIGS. 4D–4F, since the rising edge of the clear signal CLR_SYNC is synchronized to, and nearly aligned with, the rising edge of the clock signal CLK, the target flip-flops have nearly a complete clock period to respond to the clear signal (e.g., initialize their Q outputs to a logic zero) before the next rising edge of the clock signal CLK. In other words, as long as the propagation delay times T1 and T2 are both less than the clock period (which is almost always the case), both target flip-flops will be properly cleared to zero before the rising edge of the next (e.g. fourth) clock pulse.
Therefore, synchronizer 300 insures that a number of rising edge triggered flip-flops with different propagation delay times can be cleared to a known state before the rising edge of the next clock signal CLK. Similarly, by converting flip-flops FF1 and FF2 into falling edge triggered flip-flops (using inverted clock inputs), the resulting circuit insures that a number of falling edge triggered flip-flops with different propagation delay times can also be initialized to a known state before the falling edge of the next clock signal CLK.
Nevertheless, a serious limitation of synchronizer 300 is that it cannot clear rising edge triggered flip-flops and falling edge triggered flip-flops at the same time. The reason for this is that synchronizer 300 cannot synchronize the clear signal CLR_SYNC to both edges of the clock signal CLK at the same time. Thus there is a definite need for an improved synchronization circuit that can simultaneously clear rising edge triggered flip-flops and falling edge triggered flip-flops at the same time.